6,292
questions
0
votes
0
answers
11
views
How to Configure FPGA via CPLD Flash Programming for PS Configuration Scheme?
I am a beginner with CPLD and Verilog. I’m working on a project where I need to configure an FPGA using CPLD Flash programming for a Processor System (PS) configuration scheme. According to the ...
-1
votes
0
answers
22
views
I have a timing issue in the SystemVerilog verification environment I built for memory. I need help, please [closed]
Synchronization issue between the monitor_in and monitor_out, and the results in the scoreboard. I'm attaching a link to EDA Playground.
https://www.edaplayground.com/x/nx3g
I tried adding conditions ...
0
votes
1
answer
52
views
Static vs. automatic tasks
I'm trying to understand static tasks. Here I understand that Thread1, 2 & 3 occur concurrently and that _time & t_name are static variables inside the task. When I simulate the code, I get:
[...
- 19
0
votes
0
answers
57
views
VerilatedFstC variables wrapped with std::unique_ptr crashed when the program exits
I'm working with verilator using c++, I wrote the following test code:
#include "Vmux_2_1.h"
#include <memory>
#include <verilated.h>
#include <verilated_fst_c.h>
std::...
- 9
1
vote
1
answer
42
views
Why do I get a syntax error using the ternary operator with function calls?
I'm writing a code in SystemVerilog, and I'm trying to use the ternary operator to decide between two function calls. Here's my code:
module tb;
int a = 1, b = 4;
initial begin
b > a ? $...
- 105
1
vote
1
answer
27
views
Xilinx Vivado 2023 IP block design issue: Unable to connect output of RTL module to AXI GPIO output that is connected to LED
I am using Vivado 2023.1, and I am not able to connect the output of the RTL module to the AXI GPIO output that is connected to the LED. Please take a look at the attachment. RTL is below
module ...
- 467
2
votes
1
answer
31
views
Verilog port mapping when a gate netlist module's vector ports instatantiated inside an rtl module have been split into each bit by P&R tool
I have to run an rtl simulation where all the source codes are verilog (system verilog) files but a module of my interest is a gate netlist module. Of course I have to put some wire delays around the ...
- 5,739
-1
votes
0
answers
24
views
User Testbench for Core1553BRT_APB in LiberoSoc
In LiberoSoc IDE I'm trying to simulate a remote terminal of the MIL-STD-1553B interface using the IP core Core1553BRT_APB. For this i'm using the User Testbench provided by this core. When I launch ...
- 1
-1
votes
0
answers
16
views
Using Octal SPI to transfer data between two FPGA chips [closed]
I want to use Octal SPI as the data transmission interface between two FPGA chips.
But I found that Octal SPI is mainly used to expand flash, and there are few applications of using it as a data ...
1
vote
2
answers
58
views
Verilog assignment using vectors
I am attempting to assign data from one wire to another wire in Verilog using vector subscripting. This is the simplest implementation that I could think to write to demonstrate the problem I have. ...
- 73
-1
votes
0
answers
26
views
Verilog says that there are "No top level modules, and no -s option."
I'm a beginner to Verilog, and when I try to run this basic program like this, it does not seem to work. Can anyone help? For context, I run Ubuntu 22.04.4 and used "sudo apt install iverilog&...
0
votes
1
answer
82
views
UART communication on FPGA doesnt work as expected at designated BAUDRATE [closed]
I have a UART Communication system with my FPGA where I have set my FPGA at a Baudrate of 9600. Unfortunately when I try to send data test data I send from my laptop to my FPGA at Baudrate of 9600 I ...
- 21
-1
votes
0
answers
30
views
How does packages in Bluespec system verilog share interfaces and how do they communicate if they have same interface?
How do the packages in Bluespec System Verilog communicate with each other ? Let us say, for example,
interface PutIfc ;
method put ;
endinterface
interface GetinfoIfc ;
interface PutIfc ;
...
- 1
-1
votes
0
answers
39
views
Data not being sent correctly when using array
I have the following module for a Nokia 5110 lcd display. Right now it basically initializes the screen and turns all pixels on.
module FSM_pet (
input clk, // sys. clk
input ...
-2
votes
0
answers
39
views
What should i change or add to make this 8 bit in and 1 bit out
module fifo #(parameter DEPTH = 1024, DATA_WIDTH=8) (
input clk, srst,
input wr_en, rd_en,
input [DATA_WIDTH-1:0] din,
output reg [DATA_WIDTH-1:0] dout,
output full, empty
);
reg [DEPTH-...
